ADX320QAQFN32
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Automotive-grade, single-channel, synchronous 24-bit high-precision ADC
Product details
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Parameters
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Characteristics
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Package
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Description
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1 PGA, 1 24-bit high-precision ADC, SPI communication, sampling rate 16Ksps
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-40°C ~ +125°C
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• AEC-Q100
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Operating temperature range
−40°C ~ 125°C
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• Two PGAs and a high-precision ADC on-chip
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• Data rate
125SPS ~ 6kSPS
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• Programmable gain: 1, 2, 3, 4, 6, 8, or 12
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• Input bias current 100pA (max)
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• Power supply: Single or bipolar
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– Analog: 2.7V to 5.5V – Digital: 1.65V to 3.6V
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• Internal bias amplifier
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• Sensor disconnection current detection
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• Flexible power consumption modes
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• Built-in oscillator and reference
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• Power monitor, internal temperature sensor, OSC failure detection, over-range detection
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• Flexible power-down, standby modes
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• SPI™ compatible serial interface, timeout reset
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• Communication cyclic redundancy check (CRC), checksum ADC data FIFO maximum depth 24 sampling data
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• Functional safety
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• QFN-32 package
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QFN32 4mm x 4mm
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The ADX320Q/ADX3202Q is a single/dual-channel, simultaneously sampling, 24-bit, Δ-Σ (Delta-Sigma) analog-to-digital converter (ADC) offering wide dynamic range, low power consumption, and buffered analog inputs, making it highly suitable for automotive battery management systems (BMS). The ADC inputs can be directly connected to shunt resistors for bidirectional battery current measurement, resistor divider networks for high-voltage measurement, or temperature sensors such as thermistors or analog output temperature sensors. Each ADC channel can be independently configured according to the sensor input. The low-noise, programmable gain amplifier (PGA) provides gain from 1 to 12 to amplify low-level signals. This device features a global chopping mode that eliminates offset drift over temperature and time. Moreover, the device integrates offset and gain calibration registers to help eliminate signal chain errors. It also incorporates a low-drift 2.4V or 4.2V reference and a precision oscillator, reducing the printed circuit board (PCB) area. Optional cyclic redundancy check (CRC) on data input, data output, and register map maintains communication integrity.
